The present invention generally relates to semiconductor device manufacturing, and more particularly to the formation of fins with multiple threshold voltages using (3D) condensation.
FinFET, Tri-Gate, and nanowire devices typically include a non-planar multiple gate transistor device. The device includes a conducting channel disposed on a silicon fin, nanowire, or similar linear structure.
Complementary metal oxide semiconductor (CMOS) devices exhibit a threshold voltage (Vt). A voltage applied to the gate of an n-type device (gate voltage) that equals or exceeds the threshold voltage induces a low resistance conductive path between the source and drain regions of the device. While a gate voltage that is below the threshold voltage results in little or no conductive path between the source and drain regions.
In electronic circuits, devices with different threshold voltages are used to realize circuit function. Previous methods of fabricating multiple devices with different threshold voltages included implanting different types of substrate dopants for FET devices that result in different threshold voltages.